1. Technical Field
The present disclosure relates to a current mirror circuit. The disclosure will make reference to the field of non-volatile memory devices, in particular PCM (Phase Change Memory) devices, without this implying any loss in generality.
2. Description of the Related Art
As is known, PCM devices include an array of memory cells connected at the intersections of bitlines and wordlines and comprising each a memory element. The memory element comprises a phase change region made of a phase change material, i.e., a material that may be electrically switched between a generally amorphous and a generally crystalline state across the entire spectrum ranging between a completely amorphous and a completely crystalline state; as phase change materials, various chalcogenide elements are commonly used. The state of the phase change material is non-volatile, absent application of excess temperatures, such as those in excess of 150° C., for extended times. When the memory is set in either a crystalline, semi-crystalline, amorphous, or semi-amorphous state representing a resistance value, that value is retained until reprogrammed, even if power is removed. Phase changes are obtained by locally increasing the temperature of the memory element by means of resistive electrodes (generally known as heaters) in contact with the chalcogenide element.
Current mirror circuits are widely used in such non-volatile memory devices, in particular in sense amplifiers stages thereof, and allow to perform memory operations on the individual memory cells, like reading or verify during programming (either during writing or erasing).
FIG. 1 shows a schematic block diagram of a portion of a known non-volatile memory device (e.g., a PCM memory device), denoted in general with 1, made in a die 2 (shown schematically) of a semiconductor material.
A reference current Iref is generated in a periphery portion 2a of the die 2 by means of a reference current generator 3 and routed towards a core portion 2b of the same die 2, in which memory partitions Pi of the memory device 1 are made, via a reference current bus. Each memory partition Pi includes a respective current mirror 4, that is connectable to the reference current bus via a respective connecting switch 5. Each current mirror 4 has a reference branch (including a first, diode-connected, MOS transistor 6) connectable to the reference current bus via the respective connecting switch 5 and receiving therefrom the reference current Iref, and a plurality of mirrored branches (including respective second MOS transistors 7) connected to respective sense amplifier stages (here not shown in detail and denoted with reference SA), the number of the sense amplifier stages SA being dependent on the number of memory cells making up each memory partition Pi. Current mirrors 4 allows the local generation of replicas of the reference current Iref at each memory partition Pi, to be supplied to the sense amplifier stages SA for performing memory operations.
Routing of current reference Iref, instead of a voltage reference, is advantageous to avoid ohmic losses occurring along the reference current bus (and consequent variations in the reference quantity supplied to the various memory partitions Pi), but entails higher power consumption. In particular, generation of reference currents having lower values (to reduce the above power consumption) is not practical, because disturbance factors, such as parasitic capacitance or charge injection due to switching of the transistors, must be taken into account, and the locally generated replicas of the reference currents should have mismatch errors preferably lower than 5%; as a consequence, high polarization reference currents are indeed needed in such current mirror circuits.
In particular, power consumption should be reduced as much as possible when a memory partition Pi is deselected or put in stand-by (i.e., in any condition in which the memory cells of the partition are not involved in memory operations). Moreover, the time for exiting from the stand-by (or deselected) condition should be as low as possible, in order for the same memory cells to be readily available for next memory operations. This implies that start-up of the current mirrors should be enhanced, in order to reduce re-activation delays.
Current-mirror circuit arrangements have already been proposed to achieve efficient stand-by management, for example including dedicated start-up circuits facilitating transition from a stand-by to an operating state. However, these circuits have not proven to be fully satisfactory, in particular as far as the requirements of low power-consumption or low mismatches are concerned.